Registers On Demand, an integrated region scheduler and register allocator
نویسندگان
چکیده
Two of the most important phases of code generation for instruction level parallel processors are register allocation and instruction scheduling. Applying these two phase separately has major drawbacks like the introduction of false dependences, or a higher register pressure and thus more spill code. In this paper we present a new method which integrates register allocation and region scheduling, called Registers on Demand. We discuss register selection, spilling and the insertion of state preserving code around function calls. We have implemented the new method and compared its results with two early assignments methods. From the experiments we conclude that our method gives good results, in particular for applications for which registers are a critical resource. Therefore we propose that future ILP compilers should incorporate integrated instruction scheduling and register allocation. Registers On Demand, an integrated region scheduler and register allocator Abstract Two of the most important phases of code generation for instruction level parallel processors are register allocation and instruction scheduling. Applying these two phase separately has major drawbacks like the introduction of false dependences, or a higher register pressure and thus more spill code. In this paper we present a new method which integrates register allocation and region scheduling, called Registers on Demand. We discuss register selection, spilling and the insertion of state preserving code around function calls. We have implemented the new method and compared its results with two early assignments methods. From the experiments we conclude that our method gives good results, in particular for applications for which registers are a critical resource. Therefore we propose that future ILP compilers should incorporate integrated instruction scheduling and register allocation.Two of the most important phases of code generation for instruction level parallel processors are register allocation and instruction scheduling. Applying these two phase separately has major drawbacks like the introduction of false dependences, or a higher register pressure and thus more spill code. In this paper we present a new method which integrates register allocation and region scheduling, called Registers on Demand. We discuss register selection, spilling and the insertion of state preserving code around function calls. We have implemented the new method and compared its results with two early assignments methods. From the experiments we conclude that our method gives good results, in particular for applications for which registers are a critical resource. Therefore we propose that future ILP compilers should incorporate integrated instruction scheduling and register allocation.
منابع مشابه
Fast, frequency-based, integrated register allocation and instruction scheduling
Instruction scheduling and register allocation are two of the most important optimization phases in modern compilers as they have a significant impact on the quality of the generated code. Unfortunately the objectives of these two optimizations are in conflict with one another. The instruction scheduler attempts to exploit ILP and requires many operands to be available in registers. On the othe...
متن کاملOptimistic Integrated Instruction Scheduling and Register Allocation
Instruction scheduling and register allocation are two fundamental operations used in an optimizing compiler’s back-end. There is a well-known phase ordering problem between these two stages: Performing either stage first can result in intermediate code that forces the other stage to make suboptimal decisions. We propose an optimistic integrated approach in which scheduling is performed before ...
متن کاملA scheduler-sensitive global register allocator
Compile-time reordering of machine-level instructions has been very successful at achieving large increases in performance of programs on machines ooer-ing ne-grained parallelism. However, because of the interdependences between instruction scheduling and register allocation, it is not clear which of these two phases of the compiler should run rst to generate the most eecient nal code. In this ...
متن کاملRegister Allocation over the Program Dependence Graph Cindy
This paper describes RAP, a Register Allocator that allocates registers over the Program Dependence Graph (PDG) representation of a program in a hierarchical manner. The PDG program representation has been used successfully for scalar optimizations, the detection and improvement of parallelism for vector machines, multiple processor machines, and machines that exhibit instruction level parallel...
متن کاملRepresenting Architecture Constraints in Ursa
Architectural features such as pipelines, instructions that use registers implicitly, and instructions that can be executed on any of several types of functional units require a tightly integrated instruction scheduler and register allocator. Such an integrated system can detect the interactions between the various problems that must be solved and therefore improve the use of available resource...
متن کامل